Reduction of Power in Phase unwrapping algorithm using RCA

Fathima Beevi M, Saju A, Vishnu Raj

Page No: 45-56

DOI: 10.86493/VEREDAS.2023/V13I3/05

The paper presents a phase unwrapping architecture for imaging applications. The architecture is that theimplementation of a path-independent non-iterative Discrete Cosine Transform (DCT) based minimum mean square algorithm for accurate and fast phase unwrapping. The implementation is based on field programmable gate array. The architecture is able to exploit the parallelism among different stages of the algorithm for maximizing the throughput of the computation. To reduce the power a Ripple Carry Adder (RCA) is used. As compared with other implementations for fast phase unwrapping, the proposed architecture has the advantages of high throughput, high accuracy, and low power consumption. It is designed using Verilog HDL and is implemented using Xilinx 14.2 ISE tools.

Citations

APA: Fathima Beevi M, Saju A, Vishnu Raj (2025). Reduction of Power in Phase unwrapping algorithm using RCA. DOI: 10.86493/VEREDAS.2023/V13I3/05

AMA: Fathima Beevi M, Saju A, Vishnu Raj. Reduction of Power in Phase unwrapping algorithm using RCA. 2025. DOI: 10.86493/VEREDAS.2023/V13I3/05

Chicago: Fathima Beevi M, Saju A, Vishnu Raj. "Reduction of Power in Phase unwrapping algorithm using RCA." Published 2025. DOI: 10.86493/VEREDAS.2023/V13I3/05

IEEE: Fathima Beevi M, Saju A, Vishnu Raj, "Reduction of Power in Phase unwrapping algorithm using RCA," 2025, DOI: 10.86493/VEREDAS.2023/V13I3/05

ISNAD: Fathima Beevi M, Saju A, Vishnu Raj. "Reduction of Power in Phase unwrapping algorithm using RCA." DOI: 10.86493/VEREDAS.2023/V13I3/05

MLA: Fathima Beevi M, Saju A, Vishnu Raj. "Reduction of Power in Phase unwrapping algorithm using RCA." 2025, DOI: 10.86493/VEREDAS.2023/V13I3/05